This invention relates generally to the field of amplifiers and more particularly to high gain amplifiers.
Known wireless telephones include, but are not limited to, analog telephones using analog transmission formats, such as circuits using the AMPS standard, and to digital telephones using digital transmission formats, such as TDMA (time division multiple access) applications, including, but not limited to standards such as IS-136, GSM and next generation (xe2x80x9cG3xe2x80x9d) wireless telephone standards.
Increased battery life is one of the advantages that digital wireless telephones have over analog wireless telephones. For example, while in a standby mode (such as when the telephone is on, but not engaged in a telephone call), an analog telephone typically continuously monitors channels that are available for incoming telephone calls. Also, during a wireless telephone call, the receive circuit of an analog telephone is typically continuously receiving a telephone transmission.
Digital telephones, on the other hand, may be xe2x80x9cpowered downxe2x80x9d for predetermined periods, conserving battery power and extending battery life. For example, while in standby mode, a digital wireless telephone, such as one using a TDMA format, typically activates the receive circuitry for only one or two timeslots of a frame of available timeslots. Similarly, during a wireless telephone call, the receive circuit of a digital telephone typically receives a telephone transmission only during predetermined timeslots of a frame of available timeslots. During inactive timeslots, the receive circuitry may be put in a low-power state, to conserve power.
In any TDMA application, time is divided up into frames having discrete timeslots. For example, in GSM the TDMA frame is approximately 4.6 milliseconds long. In GSM each frame is divided into 8 timeslots of approximately 577 micro seconds each. In every frame, one or two timeslots are used for receiving and one or two timeslots are used for transmitting.
The transition from a low-power state to an active state is not necessarily instantaneous. Accordingly, the time required to bring the receive circuitry from a low-power state to an active state is one of the considerations in designing receive circuitry. The shorter the time to transition from the low-power state to the active state, the longer the low-power state may be maintained, so as to enhance battery life.
Another consideration in designing receive circuitry for digital telephones is the amplification of received signals prior to analog to digital conversion. Typically, received signals are amplified by a high gain receiver chain having one or more stages of high gain amplifiers. One of the problems in such a high gain receiver chain may be the presence of direct current (xe2x80x9cDCxe2x80x9d) offsets. Such DC offsets, if uncorrected, may be amplified to the level where the DC offsets would saturate one or more of the stages of the high-gain receiver.
DC offsets in high gain receiver chains may be caused by offsets that are unintentionally built in to the receiver due to mismatches in the devices used in the receiver circuitry. DC Offsets may also be caused by the coupling of local oscillator (LO) input signals to the radio frequency (RF) port. Coupling of large RF input signals to the LO port may also cause DC offsets, but such offsets are more difficult to correct due to the varying of RF signal strength.
In a digital wireless telephone, a typical receiver may include an antenna, coupled by an amplifier to a direct conversion mixer, which is in turn coupled by a high-gain receiver amplifier to one or more analog to digital converters (AID converters). A direct conversion mixer mixes a radio-frequency (RF) signal with a local oscillator (LO) signal to shift modulated channels, which are centered at RF frequencies when received, so that they are centered around a direct current (DC) reference. Alternatively, a receiver circuit may include an RF to intermediate frequency (IF) converter, with the RF to IF converter coupled to an IF to baseband mixer.
The output at low frequencies is referred to as a baseband signal. The baseband outputs of a receiver are typically required to be quadrature (phases differing by 90 degrees) so that they are able to convey the phase information in-phase modulated channels. The I (in-phase) signal and Q (quadrature phase) signal are the baseband signals,
Further amplification of the I and Q signals is typically performed before these signals can be input to the AID converters. An undesirable aspect of the amplification of the I and Q signals is the amplification of any DC offsets that may be present at the I and Q outputs of the mixer. The high-gain receiver chain may also add its own DC offsets due to mismatch in the circuitry that forms the baseband amplifiers.
After amplification, the I and Q baseband signals are then input to the A/D converters. The A/D converters form the input stages to the digital processing circuitry that comprises the coding and decoding sections of modem digital telephones. The signals are demodulated in the digital sections.
Also, a high gain receiver amplifier, or chain of amplifiers, typically is designed with limited bandwidth. The high gain receiver amplifier is typically filters out undesirable signals that may have been mixed down with the desired radio signal. The settling time of a chain of amplifiers in the high gain receiver amplifier is inversely proportional to its bandwidth. Thus, the narrower the bandwidth, the longer the settling time. In high gain receiver amplifiers used in typical wireless telephone applications, bandwidths are relatively narrow leading to relatively long settling times. However, because TDMA time slots are of finite duration, an amplifier chain needs to settle down an d be corrected for DC offset within a reasonable time.
In order to eliminate the DC offsets, in TDMA based systems, it is known to include circuitry that measures the DC offsets and provide correction control voltage information that is stored on a discrete holding capacitor during the receiving TDMA slot. Previous solutions have used an external, discrete holding capacitor. The additional holding capacitors, however, add expense to a wireless telephone and occupy area on a circuit board, which runs contrary to design goals to lower the cost and reduce the size of wireless telephones. Also, the prior solution does not address the long settling time for amplifiers having narrow bandwidth filters.
An amplifier chain with sequential DC offset correction for use in a radio receiver is provided. The amplifier chain has at least first and second amplifier stages connected in series. The first and second stages include an amplifier and a track and hold circuit connected in parallel across the amplifier. The track and hold circuit has a tracking state and a holding state. A control signal is coupled to the track and hold circuits of the first and second stages. The control signal is configured to set the track and hold circuits to the tracking state, which may be done simultaneously, and to sequentially set the track and hold circuit of the first stage to the holding state and then set the track and hold circuit of the second stage to the holding state.
In one example, the track and hold circuit may be an analog circuit having a holding capacitor and an amplifier. The amplifier has a tracking input coupled to the stage output and a tracking output selectively coupled to the holding capacitor when the track and hold circuit is in the tracking state. A buffer is connected to the holding capacitor, and is selectively coupled to the stage input when the track and hold circuit is in the holding state. In another example, the track and hold circuit may be a digital circuit having a comparator, a counter, a digital to analog converter and a data register. The comparator has a first input connected to a DC offset current from the amplifier stage, a second input, connected to a reference signal, and an output. The counter has an input coupled to the output of the comparator and a correction current output. The digital to analog converter has an input connected to the output of the counter and an output connected to the first input of the comparator and summed with the DC offset current from the amplifier stage. The data register is connected to the output of the counter.
In another embodiment, one or more stages of the amplifier chain may include a low pass filter having a narrow bandwidth state and a high bandwidth state coupled in series with the amplifiers. A high bandwidth control signal is coupled to the low pass filter, and is capable of setting the low pass filter to the high bandwidth state during DC offset correction to reduce settling time.
Other systems, methods, features and advantages of the invention will be or will become apparent to one with skill in the art upon examination of the following figures and detailed description. It is intended that all such additional systems, methods, features and advantages be included within this description, be within the scope of the invention, and be protected by the accompanying claims.